Fix cache_access
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parent
9997f58137
commit
e457f4dee0
16
csim.c
16
csim.c
@ -234,17 +234,13 @@ char cache_access(linked_line** cache, long address, int set_bits, int block_bit
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else if (line->tag == tag) out = 'H';
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else out = 'E';
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if (line != set_head) {
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line->newer = NULL;
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set_head->newer = line;
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line->older = set_head;
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if (line->older) {
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if(!(line == set_head)) {
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line->newer->older = line->older;
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if(line->older)
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line->older->newer = line->newer;
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if (line->older->older == line)
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line->older->older = NULL;
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}
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if (line->newer)
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line->newer->older = line->older;
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line->newer = NULL;
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line->older = set_head;
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set_head->newer = line;
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cache[set] = line;
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}
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